Flux-driver circuit for phased array

ABSTRACT

A flux driver circuit supplies a pair of control pulses to a magnetically controlled analogue microwave phase shifter used in a phased array antenna system. The flux driver circuit system first delivers a reset pulse which drives the magnetic material to saturation in one direction and then supplies a set pulse which drives the magnetic material in the opposite direction and to a predetermined desired flux level. When the radar system changes from the transmit to the receive mode and a new predetermined flux level is desired in the phase shifters, the reset-set cycle is again repeated. The level of magnetic flux in the phase shifter is controlled by a D.C. command voltage supplied to the circuit. Provision is made for reversing the polarity of the applied reset-set voltage when switching the antenna between the transmit and the receive modes.

[ 1 Oct. 17, 1972 FLUX-DRIVER CIRCUIT FOR PHASED ARRAY PrimaryExaminer-J. D. Miller Assistant Examiner-Harry E. Moose, Jr.

[72] Inventor: John H. Kuck, Silver Spring, Md. Anmey R. S- Sciasica Q.E Hodges and J. I [73] Assignee: The United States of America asRosenblatt represented by the Secretary of the Navy [57] ABSTRACT [22]Filed: March 30, 1971 A flux driver circuit supplies a pair of controlpulses to a magnetically controlled analogue microwave phase [21] Appl129312 shifter used in a phased array antenna system. The flux drivercircuit system first delivers a reset pulse [52] US. Cl ..317/l23,3l7/DIG. 4, 317/148, which drives the magnetic material to saturation in343 100 SA, 343 354 one direction and then supplies a set pulse which 51Int. Cl. ..H0lh 47/22 drives the magnetic material in the pp direction[58] Field of Search ..3l7/DIG. 4, 148, 123; and to a predetermineddesired flux level when the 343/100 SA, 854, 754 radar system changesfrom the transmit to the receive mode and a new predetermined flux levelis desired in R f d the phase shifters, the reset-set cycle is againrepeated. [56] e erences e The level of magnetic flux in the phaseshifter is con- UNITED STATES PATENTS trolled by a DC. command voltagesupplied to the circuit. Provision is made for reversing the polarity ofthe H 2/1958 McLean et a1 17/148 X applied reset-set voltage whenswitching the antenna 3,237,088 2/1966 Karp et a1. ..3l7/DIG. 4 betweenthe transmit and the receive modes. 3,438,044 4/1969 Elia et al..343/854 3,484,785 12/1969 Sheldon et al. ..343/854 X 15 Claims, 2Drawing Figures I Zi Zi IT 1 |3 i I i4 43 I 2o 39 23 I I 25 I AND ORSELECTOR OR I VOLTAGE i 'NTEGRATOR COMPARATOR GATE GATE I SWITCH GATE IAMPLIFIER U I l l I J L I I ll I i 1 l DUMP .FL .FL i i CIRCUIT 3 5-;(TRAILING EDGE) i C i l Jl i T l l I l SELECTOR 37 3. OR I L SELECTOR 0Ri i VOLTAGE n SWITCH at GATE i I SWITCH GATE I I AMPLIFIER I R I(LEADING EDGE) I V I I I A l5 [7 L l l |L I T c I T R 7 27./ I SELECTORmi/E T iER SWITCH *2 29 2s I R l i l i f 33 L A B PHASE SHIFT PHASESHIFT DRIVER DRIVER 1 I FERRITE PHASE SHIFTERS PATENTEDncI 11 m2 SHEET 2BF 2 INVENTOR.

JOHN H. KUCK I '/'I ATTORNEY FLUX-DRIVER CIRCUIT FOR PI-IASED ARRAYBACKGROUND OF THE INVENTION Non-reciprocal magnetic phase shifters arewidely used in phased array antenna systems. These nonreciprocal phaseshifters must be reset between the transmit and receive modes. Aprovision must be made therefore, for reversing the polarity of thepulse pairs when switching the antenna between the transmit and receivemodes.

SUMMARY This invention relates to a flux driver circuit for supplyingcontrol pulses to the magnetically controlled analogue microwave phaseshifters employed in a phased array antenna system. The function of thedriver circuit is to deliver two closely spaced constant voltage pulsesof opposite polarity to a magnetically controlled analogue microwavephase shifter. The pulses must be of proper durations so that themagnetic material in the phase shifter is first driven into saturationin one direction by the reset pulse and is then driven in the oppositedirection with a variable pulse width set pulse. The width of thevariable pulse width set pulse is proportional to a level of D.C.command voltage corresponding to the predetermined flux level to beestablished in the phase shifter. A microwave phase shift introduced bythe phase shifter is a function of the magnetic flux and is therefore afunction of the command voltage too.

The flux driver circuit may be summarized as follows. At the inceptionof any mode, i.e., transmit or receive, a reset gate pulse is externallydelivered to the flux driver circuit. The reset gate pulse is channeledthrough a reversing switch to either one of two parts of a voltageamplifier. The voltage amplifier, responsive to the alignment of thereversing switch and to the reset gate pulse delivers a pulse of theappropriate positive or negative polarity. Immediately after the resetgate pulse is terminated, at phase shifter saturation, a set gate pulseis applied externally to the circuit driver. As the desiredpredetermined flux level in the phase shifter is variable, a D.C.command voltage externally applied to the phase shifter is used tocontrol the degree of phase shift during the set gate pulse interval.Feedback is employed between the phase shifter and the driver circuitand the set pulse is terminated when the desired level of flux isreached within the magnetic phase shifter.

As this device is non-reciprocal, a reversing switch is used whoseswitching alignment is responsive to external signals keyed to thetransmit mode and the receive mode time intervals. The reversing switchcauses a reversal in the polarity of the reset and set pulses relativeto the polarities of these pulses during the preceeding cycle. Forexample, if the polarity happened to be positive for the reset pulse andnegative for the set pulse during the transmission mode, the reversingswitch would reverse the polarity of the voltage amplifier output sothat during the receiving mode the polarity of the reset pulse would benegative and the polarity of the set would be positive. Non-reciprocitymeans that the magnetic flux of the phase shifter must be reversed whenthe direction of propagation of RF energy to the phase shifter isreversed as in the case of transmit and receive modes.

Certain specific features of the invention include an integrator whoseinput is the voltage across the phase shifters when the set pulse isapplied. The integrator circuit delivers an output proportional to thechange in flux across the phase shifters and when the integrator outputvoltage matches the D.C. command level voltage, the set pulse isterminated.

This circuit has an advantage of being a more efficient flux driver asthe width of the reset pulse is controlled to a minimum durationnecessary to saturate the phase shifter.

Accordingly, it is one object of this invention to establishpredetermined flux levels within a phase shifter of a phased array.

It is a second object of this invention to deliver two closely spacedconstant voltages of opposite polarity to a magnetically controlledanalogue microwave phase shifter to drive the phase shifter tosaturation in one direction and then drive it to a predetermined fluxlevel in the opposite direction.

It is a third object of this invention to reverse the polarity of theset and reset pulses between the receive and transmit modes.

It is a fourth object of this invention to control the width of thevariable set pulse in the predetermined level of flux in the phaseshifter by means of an external applied D.C. command voltage.

These and other objects of the invention will accordingly become evidentwhen the following description of the preferred embodiment is read.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 shows the flux driver in blockdiagram. FIG. 2 is a time diagram of the outputs of the circuit elementsshown in the FIG. 1 block diagram.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIGS. 1 and 2,the flux driver will be described with reference to its operation andthe operation of its particular elements, shown in the block diagram ofFIG. 1, and whose outputs are shown in the time diagram of FIG. 2. Theflux drivers basic components are the set generator, enclosed by the boxin dashed lines and designated generally by the numeral 1, the resetgenerator, enclosed by the box in dashed lines and designated generallyby the number 2, the reversing switch, enclosed by the box in dashedlines and designated generally by the numeral 3 and the voltageamplifier 4, enclosed by the box in dashed lines.

As a starting point in time for the purpose of explaining thisinvention, the onset of the radar system's transmit mode is chosen as tThe flux level of the phase shifters during the preceeding receive modeis modified and reset to a desired transmission level mode in two steps(1) a reset gate pulse is generated to drive the phase shifters intosaturation and then a set pulse is generated to drive the phase shifters.to the predetermined flux level for transmission. Saturation isattained by generating a reset gate pulse signal at t as shown in line Aof FIG. 2, and by inputting the reset gate signal into a dump circuit11. Dump circuit 11, triggered by reset gate pulse erases the memory" ofintegrator 13, and brings the output of integrator 13, shown in line Fof FIG. 2, to zero. The reset gate pulse is simultaneously fed into thereset generators differentiating circuit 15, which generates a pulsecoincident with the reset gate pulse leading edge at t (shown in line Bof FIG. 2). The output of differentiator 15, is inputted to the resetgenerators or gate 17. Or gate 17, responsive to the pulse generates apulse (shown in line C of FIG. 2). The output ofor gate 17, is fed inparallel to differentiator 19, which emits a pulse at t.,, FIG. in lineD of FiG. 2, in response to the trailing edge of the gate pulse, and tothe selector switch 21, within the reversing switch 3. The selectorswitch 21 is programmed during the transmit mode to switch the or gatesignal from gate 17 to or gate 23. The signal pulse from or gate 23 isthen inputted to voltage amplifier 25, which emits a negative goingreset pulse (line E of FIG. 2) through bus 27, (line I of FIG. 2) tophase shifter drivers 29 in parallel.

The negative going pulse shown in FIG. 2, lines E and I, produces acorresponding voltage at the monitor output 31, of the phase shiftdriver. This monitor output is channeled to phase inverter 33, whichproduces a signal of positive polarity appropriate to keep or gate 17turned on. Selector switch 35 is programmed in the transmit mode toconnect input terminal A to output terminal C. Selector switch 35 isprogrammed during the transmit mode so the signal from the phase shiftdrivers 29 is channeled through the phase inverter to or gate 17. Thesignal from the phase shift driver monitor output 31 then maintains orgate 17 on, after the termination of the reset pulse at t and untilsaturation of the phase shifters is attained at t,,.

At the point of saturation the impedance of the phase shifters will beapproximately zero and the voltage across the phase shifter will also beapproximately zero, as will be the signal at the input to or gate 17.This approximately zero signal at the phase shifter is below the or gatethreshold and turns or gate 17 off, terminating the reset pulse fromvoltage amplifier 25, at time Differentiator 19, producing a pulse(shown in line D of FIG. 2) at the trailing edge of the signal from orgate 17 at t, is fed into or gate which produces a narrow width pulse.This pulse is connected to or gate 41, through programmed selectorswitch 39, producing a spike at the output set voltage amplifier 26(line H of FIG. 2) and on line 27 (line I of FIG. 2). The spike at theoutput of voltage amplifier 26 is seen immediately after the terminationof the reset pulse at is useful in the transition between the reset andset opposite polarity pulses.

Immediately after the reset pulse drives the phase shifter to saturationand the spike (shown in line H) is produced at the output of voltageamplifier 26, the set gate pulse is initiated and fed into the input ofand" gate 43, of set generator 1. A D.C. level is maintained at theinput to comparator 45. This D.C. level is proportional to the fluxlevel to be generated in the phase shifter during the set pulse cyclefor the transmission mode. The comparator is a digital device producinga signal when the output of the integrator is less than the D.C. setcontrol voltage and producing no signal when the output of integrator 13is equal to the D.C. set control voltage. As shown in line F of FIG. 2,at t when the reset gate pulse brings the output of the integrator tozero, the output of comparator 14 undergoes a step increase at trepresenting a digital change from 0 to l After t a 1" output signalappears at the output of comparator 14, as shown in line G of FIG. 2.

The and gate 43, responsive to the set gate pulse shown in line A ofFIG. 2, at 1 and comparator 1" output (line G of FiG. 2) produces apulse signal at its output (line J of FIG. 2) which is fed into or" gate20. Or gate 20 output is fed to selector switch 39, of reversing switch3, programmed during the transmit mode to direct the signal pulse fromor gate 20 to or gate 41. The signal output from gate 41, shown in lineK, is fed into voltage amplifier 26, which produces a set output pulseshown in lines H and I of FIG. 2. This positive pulse is conveyed on bus27, (shown in line I of FIG. 2 at t to phase shifter drivers 29,connected in parallel. Selector switch 37 is programmed during thetransmit mode to transmit the positive going pulse at the monitor output31 of the phase shifter drivers, from terminal A to terminal C, throughto the integrator 13. The output of integrator 13 (shown in line F),being I edt over the time period t to t is shown in line F of FIG. 2.Comparator 45, as explained, is a digital device and has a digitaloutput signal 1 (shown in line G of FIG. 2) for as long as the output ofintegrator 13 is less than the D.C. set control voltage (shown in line Fof FIG. 2). At t when the output of integrator 13 reaches the level ofthe D.C. set control voltage the comparator digital output returns to 0,turning off the signal fed to and gate 43, turning off and gate 43 andor gate 41 and ultimately turning off the set pulse from voltageamplifier 26. The level of flux in the phase shifter is now proportionalto the D.C. level of the set control voltage and the phase shift inducedby the phase shifters will be the phase shift required to produce thedesired effect in the radar beam during the transmit mode.

At termination of the transmit mode at t a reset pulse is once againgenerated to saturate the phase shifters preparatory to driving thephase shifters to the level of flux required during the receiving mode.The system is seen to function in establishing the flux levels for thereceive mode as explained above in connection with the transmit mode.The differences are that the reset and set pulse polarities are reversedin relation to those generated in the transmit mode.

The reset gate pulse generated aft is inputted to dump circuit 11, as inthe transmit mode. The dump circuit, as explained above, erases thememory of integrator 13, and this may be done simply by shorting theoutput of integrator 13 to ground. Differentiator 15, generates a pulsein response to the leading edge of the reset pulse shown in line B at tThe pulse is fed into or gate 17, which produces a pulse shown in lineC, fed in parallel to differentiator 19, and selector switch 21 ofreversing switch 3. Selector switch 21 is programmed during the receivemode to channel the pulse of or gate 17, through to or gate 41. Or gate41 in turn generates pulse to turn on voltage amplifier 26. The outputof voltage amplifier 26 is a reset pulse as shown in line H of FIG. 2,in phase with the preceeding set pulse and which is fed to the phaseshifter drivers 29. The output of phase shifter drivers 29 produces avoltage at monitor output 31, and across the phase shifters. The voltageat monitor output 31 is fed back through feedback signal bus 28, throughprogrammed selector switch 35, to or" gate 17. Selector switch 35 isprogrammed during the receive cycle to connect the signal at terminal Bto terminal C. The output signal on feedback bus 28, channeled throughselector switch 35, maintains or" gate 17 on and maintains the output ofvoltage amplifier 26, constant until phase shifter saturation isattained. At saturation the output of the voltage across the phaseshifters drops below the threshold level of or gate 17, turning off orgate 17 and terminating the receive mode pulse at r,,.

Immediately following the termination of the reset cycle a spike ofopposite polarity to the reset pulse is generated followed by the onsetof the set pulse as explained above, in connection with the transmitmode. The D.C. set control level is adjusted during this receive cycleto be proportional to the predetermined level of flux desired in theflux driven phase shifters for the receive mode.

At the initiation of the set pulse at t the output of the integrator 13is zero, and the output of the comparator is the digital output signalI. This signal in combination with the set gate pulse turns and gate 43on and a pulse signal is generated at the output of the and gate, and atthe output ofor gate 20, shown in line J of FIG. 2. The and gate signalis channeled through selector switch 39 of reversing switch 3,programmed during the transmit mode to channel the output of or gatethrough to or gate 23. Or gate 23, generates a pulse which is fed intovoltage amplifier 25, to produce a negative going pulse at its output(line E of FIG. 2) and on bus 27 (line I of FIG. 2). This negative goingoutput is conveyed on bus 27, through to phase shifters 29 connected inparallel. The output of phase shifter driver 29, at monitor output 31,is conveyed by feedback signal bus 28, to phase inverter 33. Theinverted pulse appearing at programmed selector switch 37 is connectedfrom terminal B to terminal C, and to the input of integrator 13. Theoutput of integrator l3 begins to rise at as shown in line F of FIG. 2.When the output of integrator 13 reaches the level of the D.C. setcontrol at t,, the output of comparator 14 drops to zero, turning offand" gate 43, and turning off the set pulse for the receive mode.

At the termination point, t,, of the set pulse for the receive mode, thelevel of flux within the phase shift is at a sufficient level to givethe desired phase shift response to the received signal.

It can be seen that this apparatus can be used to change the level offlux in a magnetic phase shifter by adjusting the level of D.C. commandvoltage at the input to comparator 14. The relative polarities for theoutput of the voltage amplifier are shown for one type of phased arraywhere the direction of flux within the phase shifters are oppositerelative to the transmit and receive modes. It is seen that thepolarities of the voltage amplifiers and 26 vmay be rearranged to besuitable for the characteristics of the particular phased array usedwith this system.

Obviously many modifications and variations of the ,present inventionare possible in the light of the above teachings. It is therefore to beunderstood that within the scope of the appended claims the inventionmay be practiced otherwise than as specifically described.

What is claimed is:

1. A system for driving a non-reciprocal magnetic analogue phaseshifter, in a phased antenna array, to predetermined flux levels,comprising:

a reset generator connected to the phase shifters for driving said phaseshifters into saturation;

a set generator connected to the phase shifters for driving said phaseshifters in a reverse direction from saturation and to saidpredetermined magnetic flux level; and

said reset generator being responsive to the flux level of said phaseshifters and driving said phase shifters until said phase shifters reachsaturation.

2. The system of claim 1, including a reversing switch having an inputconnected to said set and reset generators and its output connected tosaid phase shifters for inverting the polarity of the transmission modereset and set driving signals relative to the receiving mode reset andset driving signals.

3. The system of claim 2, wherein: a control voltage is applied to saidset generator corresponding to said predetermined flux level; and

said set generator responsive to said control voltage and said phaseshifter flux level drives said phase shifters until said phase shifterflux level corresponds to said control voltage.

4. The system of claim 3, wherein said reversing switch output isconnected to a voltage amplifier; and

said voltage amplifier output being connected to said phase shifters andbeing a pulse of a predetermined polarity in response to the alignmentof said reversing switch.

5. The system of claim 4, wherein said reset generator comprises an orgate having first and second inputs;

said or gate having an output connected to said reversing switch andproviding a pulse to said reversing switch in response to a reset gatepulse at said first or gate input;

said reversing switching the output of said reset generator or gate tosaid voltage amplifier;

said voltage amplifier generator having an output pulse in response tosaid or gate pulse of a first polarity and driving said phase shifterstoward saturation;

a feedback loop connected at one end to said phase shifters andconnected at its other end to said second input of said reset generatoror gate; and

said reset generator or gate having an output in response to saidvoltage across said phase shifter until said phase shifter voltage dropsbelow said reset generator or" gate input threshold level, turning offsaid or" gate output.

6. The system of claim 5, wherein said set generator comprises anintegrator, a comparator, and an and gate;

said comparator having a first and second input;

said first comparator input being said control voltage;

said comparator having a second input connected to said integratoroutput;

said comparator output being connected to a first input of said andgate;

said integrator output going to zero in response to said reset gatepulse;

said comparator having a digital output signal corresponding to l or andhaving its l signal output when said integrator output is less than saidDC control voltage;

said and gate having an output pulse in response to said set gate pulsesignal at its first input and said comparator l output at its secondinput;

said and gate output being connected to said reversing switch;

said voltage amplifier responsive to said reversing switch alignment,delivering a pulse output opposite in polarity to said reset pulseoutput;

said feedback loop being connected to said set generator integrator;

said integrator having an output proportional to the flux level of saidphase shifter; and

said comparator output going from l to 0 when said integrator outputcorresponds to said control voltage and said predetermined flux level insaid phase shifter and turning off said set pulse. 7. The system ofclaim 6, wherein said feedback loop includes a phase inverter forinverting the phase of said voltage across said phase shifter in orderto produce a signal of proper phase to actuate said reset generator orgate and said set generator integrator.

8. The system of claim 7, including: a second or gate having first andsecond inputs; said first input being connected to the output of saidset generator and gate and said second input being connected to theoutput of a differentiator;

said differentiator having an input connected to the output of saidreset generator or gate;

said differentiator delivering a pulse in response to the trailing edgeof said reset generator or gate signal;

said or gate responsive to said differentiator signal having an outputconnected to said reversing switch; and

said voltage amplifier output being a spike, responsive to said secondor gate signal and being of opposite polarity relative to the resetdriving signal.

9. The system of claim 8, wherein said reversing switch includesselector switches programmed in response to external signalscorresponding to the trans mission and the receive mode of said antennaarray; and

said system includes a dump circuit having its output connected to saidintegrator and causing said integrator output to go to 0 in response toa reset gate pulse at said dump circuit input.

10. The system of claim 9, wherein said voltage amplifier includes:

a first voltage amplifier having a negative polarity output and saidsecond voltage amplifier having a positive polarity output;

said first voltage amplifier producing said output for driving saidphase shifters to saturation for the transmission mode and to saidpredetermined flux level for the receive mode; and

said second voltage amplifier driving said phase shifters to saidpredetermined flux level subsequent to saturation, for the transmissionmode and to saturation for said receive mode.

11. The system of claim 9, wherein said voltage amplifier includes: u

a first voltage amplifier having a positive polarity output and saidsecond voltage amplifier having a negative polarity pulse;

said first voltage amplifier producing said output for driving saidphase shifters to saturation for the receive mode and to saidpredetermined flux level for said transmission mode; and

said second voltage amplifier driving said phase shifters to saidpredetermined flux level subsequent to saturation, for said receive modeand to saturation for said transmission mode.

127 A method for producing a predetermined magnetic flux level in amagnetic analogue phase shifter in a phased array comprising the stepsof:

driving the phase shifter to saturation; and

reversing the current to said phase shifter and driving said phaseshifter to the predetermined flux level.

13. The method of claim 12, wherein said step of driving said phaseshifters to saturation includes the step of sensing the flux level ofsaid phase shifter and terminating said saturation driving current inresponse to said phase shifter reaching saturation; and

said step of driving said phase shifters to said predetermined fluxlevel including the step of sensing the flux level of said phaseshifters and terminating the current of said phase shifters when thepredetermined flux level is reached.

14. The method of claim 13, wherein said phase shifters are driven in afirst direction to saturation and said phase shifters are driven in asecond direction opposite the said first direction to establish saidpredetermined flux level.

15. The method of claim 14, including the steps of reversing thepolarity of the driving current for saturation and of the current fordriving the phase shifters to a predetermined flux level, relative tothe transmission and receiving modes.

1. A system for driving a non-reciprocal magnetic analogue phaseshifter, in a phased antenna array, to predetermined flux levels,comprising: a reset generator connected to the phase shifters fordriving said phase shifters into saturation; a set generator connectedto the phase shifters for driving said phase shifters in a reversedirection from saturation and to said predetermined magnetic flux level;and said reset generator being responsive to the flux level of saidphase shifters and driving said phase shifters until said phase shiftersreach saturation.
 2. The system of claim 1, including a reversing switchhaving an input connected to said set and reset generators and itsoutput connected to said phase shifters for inverting the polarity ofthe transmission mode reset and set driving signals relative to thereceiving mode reset and set driving signals.
 3. The system of claim 2,wherein: a control voltage is applied to said set generatorcorresponding to said predetermined flux level; and said set generatorresponsive to said control voltage and said phase shifter flux leveldrives said phase shifters until said phase shifter flux levelcorresponds to said control voltage.
 4. The system of claim 3, whereinsaid reversing switch output is connected to a voltage amplifier; andsaid voltage amplifier output being connected to said phase shifters andbeing a pulse of a predetermined polarity in response to the alignmentof said reversing switch.
 5. The system of claim 4, wherein said resetgenerator comprises an ''''or'''' gate having first and second inputs;said ''''or'''' gate having an output connected to said reversing switchand providing a pulse to said reversing switch in response to a resetgate pulse at said first ''''or'''' gate input; said reversing switchingthe output of said reset generator ''''or'''' gate to said voltageamplifier; said voltage amplifier generator having an output pulse inresponse to said ''''or'''' gate pulse of a first polarity and drivingsaid phase shifters toward saturation; a feedback loop connected at oneend to said phase shifters and connected at its other end to said secondinput of said reset generator ''''or'''' gate; and said reset generator''''or'''' gate having an output in response to said voltage across saidphase shifter until said phase shifter voltage drops below said resetgenerator ''''or'''' gate input threshold level, turning off said''''or'''' gate output.
 6. The system of claim 5, wherein said setgenerator comprises an integrator, a comparator, and an ''''and''''gate; said comparator having a first and second input; said firstcomparator input being said control voltage; said comparator having asecond input connected to said integrator output; said comparator outputbeing connected to a first input of said ''''and'''' gate; saidintegrator output going to zero in response to said reset gate pulse;said comparator having a digital output signal corresponding to''''1'''' or ''''0'''' and having its ''''1'''' signal output when saidintegrator output is less than said D.C. control voltage; said''''and'''' gate having an output pulse in response to said set gatepulse signal at its first input and said comparator ''''1'''' output atits second input; said ''''and'''' gate output being connected to saidreversing switch; said voltage amplifier responsive to said reversingswitch alignment, delivering a pulse output opposite in polarity to saidreset pulse output; said feedback loop being connected to said setgenerator integrator; said integrator having an output proportional tothe flux level of said phase shifter; and said comparator output goingfrom ''''1'''' to ''''0'''' when said integrator output corresponds tosaid control voltage and said predetermined flux level in said phaseshifter and turning off said set pulse.
 7. The system of claim 6,wherein said feedback loop includes a phase inverter for inverting thephase of said voltage across said phase shifter in order to produce asignal of proper phase to actuate said reset generator ''''or'''' gateand said set generator integrator.
 8. The system of claim 7, including:a second ''''or'''' gate having first and second inputs; said firstinput being connected to the output of said set generator ''''and''''gate and said second input being connected to the output of adifferentiator; said differentiator having an input connected to theoutput of said reset generator ''''or'''' gate; said differentiatordelivering a pulse in response to the trailing edge of said resetgenerator or gate signal; said ''''or'''' gate responsive to saiddifferentiator signal having an output connected to said revErsingswitch; and said voltage amplifier output being a spike, responsive tosaid second ''''or'''' gate signal and being of opposite polarityrelative to the reset driving signal.
 9. The system of claim 8, whereinsaid reversing switch includes selector switches programmed in responseto external signals corresponding to the transmission and the receivemode of said antenna array; and said system includes a dump circuithaving its output connected to said integrator and causing saidintegrator output to go to ''''0'''' in response to a reset gate pulseat said dump circuit input.
 10. The system of claim 9, wherein saidvoltage amplifier includes: a first voltage amplifier having a negativepolarity output and said second voltage amplifier having a positivepolarity output; said first voltage amplifier producing said output fordriving said phase shifters to saturation for the transmission mode andto said predetermined flux level for the receive mode; and said secondvoltage amplifier driving said phase shifters to said predetermined fluxlevel subsequent to saturation, for the transmission mode and tosaturation for said receive mode.
 11. The system of claim 9, whereinsaid voltage amplifier includes: a first voltage amplifier having apositive polarity output and said second voltage amplifier having anegative polarity pulse; said first voltage amplifier producing saidoutput for driving said phase shifters to saturation for the receivemode and to said predetermined flux level for said transmission mode;and said second voltage amplifier driving said phase shifters to saidpredetermined flux level subsequent to saturation, for said receive modeand to saturation for said transmission mode.
 12. A method for producinga predetermined magnetic flux level in a magnetic analogue phase shifterin a phased array comprising the steps of: driving the phase shifter tosaturation; and reversing the current to said phase shifter and drivingsaid phase shifter to the predetermined flux level.
 13. The method ofclaim 12, wherein said step of driving said phase shifters to saturationincludes the step of sensing the flux level of said phase shifter andterminating said saturation driving current in response to said phaseshifter reaching saturation; and said step of driving said phaseshifters to said predetermined flux level including the step of sensingthe flux level of said phase shifters and terminating the current ofsaid phase shifters when the predetermined flux level is reached. 14.The method of claim 13, wherein said phase shifters are driven in afirst direction to saturation and said phase shifters are driven in asecond direction opposite the said first direction to establish saidpredetermined flux level.
 15. The method of claim 14, including thesteps of reversing the polarity of the driving current for saturationand of the current for driving the phase shifters to a predeterminedflux level, relative to the transmission and receiving modes.